Input buffers are commonly used in a wide variety of digital circuits. There are also several types of input buffers. For example, there are single ended input buffers in which a single input signal is applied to the buffer to cause the buffer to transition when the input signal transitions through predetermined voltage levels. Single-ended input buffers may also compare the input signal to a reference voltage so the output of the input buffer transitions when the input signal transitions through the reference voltage. There are also complementary input buffers in which a pair of complementary signals cause the output of the buffer to transition when one of the input signals transitions through the level of the other input signal.
These types of input buffers generally perform a number of advantageous functions when used in digital circuits, such as providing a high input impedance to avoid unduly loading signal lines coupled to their inputs and conditioning signals applied to internal circuits so that internal signals have well defined logic levels and transition characteristics. Although input buffers can provide a number of advantages, they are not without limitations and disadvantages. For example, in high speed digital circuitry delays in propagating digital signals through input buffers can result in undesirable skew between an input signal applied to the buffer and an output signal from the buffer developed in response to the input signal.
Another problem that can occur with input buffers receiving complementary input signals is known as “duty cycle skew,” which is a difference between a duty cycle of the input signals applied to the buffer and an output signal generated by the buffer in response to the input signals, as will be appreciated by those skilled in the art. This type of input buffer may be formed from N-type and P-type differential amplifiers, each receiving the complementary input signals. The output of each differential amplifiers is applied to an inverter which, in response to the output from either the N-type or P-type differential amplifier, generates an output signal.
Ideally, the duty cycle skew between the input and output signals is not affected by the voltage levels and slew rates of the input signals. In an actual input buffer, however, this may not be the case. For example, due to process, voltage, or temperature variations, the “switch point” of the inverter may vary, where the switch point is the voltage level at which the inverter drives the output signal in response to the output from one of the differential amplifiers. Such a variation in the switch point of the inverter can increase the duty cycle skew introduced by the buffer, as illustrated in the signal timing diagram of FIG. 1 CLK. In FIG. 1, the top signal CLK represents the input signal applied to the buffer, the next signal down CLK1 represents the output signals from the differential amplifiers, the next signal down OCLKI represents the ideal output signal from the inverter, and the bottom signal OCLKA represents the actual output signal from the inverter. When the inverter has a first switch point SWP1, the output signal from the inverter corresponds to the ideal output signal OCLKI, and if the inverter has a second switch point SWP2 the output signal corresponds to the actual output signal OCLKA. FIG. 1 illustrate the input signal CLK and ideal output signal OCLKI having respective duty cycles defined by a time T0 while the actual output signal OCLKA has a different duty cycle defined by times T1 and T2.
There is therefore a need for an input buffer that introduces a relatively small amount of duty cycle skew, operates at a fast rate of speed, and that can be readily adapted for use as an input buffer in a wide variety of circuits and applications.